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| DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT PC8105GR 400 MHz QUADRATURE MODULATOR FOR DIGITAL MOBILE COMMUNICATION DESCRIPTION The PC8105GR is a sillicon monolithic integrated circuit designed as quadrature modulator for digital mobile communication systems. This modulator housed in a 16 pin plastic SSOP that is easy to install and contributes to miniaturizing the system. The device has power save function and can operates 2.7 to 5.5 V supply voltage to realize low power consumption. FEATURES * * * * * Internal 90 phase shifter is accurate over an IF range from 100 MHz to 400 MHz. Wide supply voltage range: VCC = 2.7 to 5.5 V. Low operation current: ICC = 16 mA (typ.). 16 pin plastic SSOP suitable for high density surface mounting. Low current in sleep mode APPLICATION * * IF modulator for Digital cellular phone (PDC, IS-54, GSM etc..) IF modulator for Digital cordless phone (PHS, PCS etc..) ORDERING INFORMATION PART NUMBER PACKAGE 16 pin plastic SSOP (225 mil) SUPPLYING FORM Carrier tape width 12 mm. Q'ty 2.5 kp/Reel Pin 1 indicated pull-out direction of tape. PC8105GR-E1 To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: PC8105GR) Caution electro-static sensitive device The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10807EJ3V0DS00 (3rd edition) Date Published October 1999 N CP(K) Printed in Japan The mark shows major revised points. (c) 1995, 1999 PC8105GR SERIES PRODUCTS PART NUMBER f LO1 in (MHz) 100 to 300 f MODout (MHz) 50 to 150 f I/Q (MHz) DC to 0.5 Up-Converter f RFout (MHz) External SERIES TYPE 150 MHz Quadrature MOD Up-Con + Quadrature MOD 400 MHz Quadrature MOD APPLICATIONS CT2, Digital Comm. PC8101GR PC8104GR PC8105GR 100 to 400 100 to 400 DC to 10 DC to 10 800 to 1900 External Digital Comm. Digital Comm. Remark: As for detail information of series products, please refer to each data sheet. INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View) LOin 1 LOin 2 GND 3 I-INPUT 4 I-INPUT 5 Q-INPUT 6 Q-INPUT 7 GND 8 90 Phase Sifter REG. 16 VCC 15 Power Save 14 GND 13 GND 12 MODout 11 N.C. 10 N.C. 9 N.C. APPLICATION EXAMPLE [Digital cellular hand-held phone] Low-noise transistor RX DEMO I Q VCO SW /N PLL PLL PC8105GR I 0 TX PA Phase shifter PC8106T 90 Q 2 Data Sheet P10807EJ3V0DS00 PC8105GR ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Power Save Voltage Power Dissipation Operating Temperature Storage Temperature SYMBOL VCC VPS PD Top Tstg RATING 6.0 6.0 310 -40 to +85 -55 to +150 UNIT V V mW C C TEST CONDITIONS TA = +25 C TA = +25 C TA = +85 C *1 *1: Mounted on 50 x 50 x 1.6 mm double copper clad epoxy glass board RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Operating Temperature Modulator Output Frequency LO1 Input Frequency I/Q Input Frequency SYMBOL VCC TA fMODout fLO1in fI/Qin DC 10 MHz MIN. 2.7 -40 100 TYP. 3.0 +25 MAX. 5.5 +85 400 UNIT V C MHz PLOin = -10 dBm PI/Qin = 600 mVp-p MAX (Single ended) TEST CONDITIONS ELECTRICAL CHARACTERISTICS (TA = +25 C, VCC = 3.0 V, Unless Otherwise Specified VPS 1.8 V) PARAMETER Circuit Current Circuit Current at Power Save Mode Output Power LO Carrier Leak Image Rejection (Side Band Leak) SYMBOL ICC ICC(PS) -21.0 MIN. 10 TYP. 16 0.1 -16.5 -40 -40 MAX. 21 5 -12.0 -30 -30 UNIT mA TEST CONDITIONS No input signal VPS 1.0 V A dBm dBc dBc PMODout LOL ImR I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) Data Sheet P10807EJ3V0DS00 3 PC8105GR STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25 C, VCC = 3.0 V, Unless Otherwise Specified VPS 1.8 V) PARAMETER I/Q 3rd Order Intermodulation Distortion I/Q Input Impedance I/Q Bias Current LO1 Input VSWR Power Save Rise Time Power Save Fall Time SYMBOL IM3I/Q MIN. TYP. -50 MAX. -30 UNIT dBc TEST CONDITIONS I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) (I I, Q Q) ZI/Q II/Q ZLO TPS(RISE) TPS(FALL) 20 5 1.2:1 2 2 5 5 k A - s s VPS(OFF) VPS(ON) VPS(ON) VPS(OFF) 4 Data Sheet P10807EJ3V0DS00 PC8105GR PIN EXPLANATION ASSIGNMENT LOin SUPPLY VOL. (V) - PIN VOL.(V) 0 PIN NO. 1 FUNCTION AND APPLICATION LO input for phase shifter. This input impedance is 50 matched internally. Bypass of LO input. This pin is grounded through internal capacitor. Open in case of single ended. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Input for I signal. This in put impedance is larger than 20 k. Relations between amplitude and VCC/2 bias of input signal are following. VCC/2 (v) 1.35 1.5 1.75 Amp. (mVp-p) *1 400 600 1000 4 EQUIPMENT CIRCUIT 1 50 2 LOin - 2.4 2 3 GND 0 - 8 - 4 I VCC/2 5 5 I VCC/2 - Input for I signal. This in put impedance is larger than 20 k. VCC/2 biased DC signal should be input. Input for Q signal. This in put impedance is larger than 20 k. VCC/2 biased DC signal should be input. Input for Q signal. This in put impedance is larger than 20 k. Relations between amplitude and VCC/2 bias of input signal are following. VCC/2 (v) 1.35 1.5 1.75 Amp. (mVp-p) *1 400 600 1000 6 Q VCC/2 - 7 Q VCC/2 - 7 6 12 MODout - 1.5 Output from modulator. This is emitter follower output. 12 *1: In case of that I/Q input signals are single ended. Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations. Data Sheet P10807EJ3V0DS00 5 PC8105GR PIN EXPLANATION ASSIGNMENT GND SUPPLY VOL. (V) 0 PIN VOL.(V) - PIN NO. 13 FUNCTION AND APPLICATION Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can be controlled ON/SLEEP state with bias as follows; VP/S (v) 1.8 to 5.5 0 to 1.0 STATE ON SLEEP EQUIPMENT CIRCUIT 14 - 15 Power Save VP/S 15 16 VCC 2.7 to 5.5 - Supply voltage pin for modulator. Internal regulator can be kept stable condition of supply bias against the variable temperature or VCC. EXPLANATION OF INTERNAL FUNCTION BLOCK 90 PHASE SHIFTER FUNCTION/OPERATION Input signal from LO is send to digital circuit of T-type flip-flop through frequency doubler. Output signal from T-type F/F is changed to same frequency as LO input and that have quadrature phase shift, 0, 90, 180, 270. These circuits have function of self phase correction to make correctly quadrature signals. BLOCK DIAGRAM from LOin x2 /2 F/F BUFFER AMP. Buffer amplifiers for each phase signals to send to each mixers. MIXER Each signals from buffer amp. are quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to good performance for image rejection. Output signals from each mixers are added with adder and send to final amplifier. I I Q Q ADDER to MODout 6 Data Sheet P10807EJ3V0DS00 PC8105GR TYPICAL CHARACTERISTICS (TA = +25 C) Unless otherwise specified VCC = VPS = 3 V, I/Q DC offset = I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p (single ended), PLOin = -10 dBm, (continuous wave) Lo INPUT POWER vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD ORDER INTERMODULATION DISTORTION 10 (PHS) 384 Kbps RNYQ 0 = 0.5 (0000) All zero -10 -10 SUPPLY VOLTAGE vs CIRCUIT CURRENT 40 35 LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc 30 Pout PMODout - Modulator Output Power - dBm -20 ICC - Circuit Current - mA 25 -20 LOL(ISO(LO)) -30 -30 20 15 -40 ImR 10 VCC = VPS = 3 V RF None -50 -40 5 -60 IM3I/Q 0 0 1 2 3 4 5 6 -70 -30 -20 -10 0 -50 +10 VCC - Supply Voltage - V PLoin - Lo Input Power - dBm Data Sheet P10807EJ3V0DS00 7 PC8105GR I/Q INPUT SIGNAL vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD ORDER INTERMODULATION DISTORTION LOL(ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBC 10 (PHS)384 Kbps RNYQ = 0.5 (0000) All zero -10 Lo INPUT FREQUENCY vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD, ORDER INTERMODULATION DISTORTION -10 Pout PMODout - Modulator Output - Power - dBm -20 ImR -30 -30 -20 -10 LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc 0 -20 PMODout - Modulator Output Power - dBm -10 Pout -20 -40 LOL(ISO(LO)) -50 -40 -30 LOL(ISO(LO)) -40 ImR -50 -30 -50 -60 IM3I/Q -60 -40 -70 50 100 200 500 -70 fLO - Lo Input Frequency - MHz -60 IM3I/Q -70 0 0.5 PI/Qin - I/Q Input Signal - Vp-p 1 -50 I/Q INPUT SIGNAL vs PHASE ERROR, MAGNITUDE ERROR, VECTOR ERROR Lo INPUT FREQUENCY vs VECTOR ERROR, MAGNITUDE ERROR, PHASE ERROR VCC = 3 V Lo: 15 dBm 10 I/Q DC 1 500 mV AC 430 mVp-p - Phase Error - deg. A - Magnitude Error - % rms M - Vector Error - % rms 5 M A - Phase Error - deg. A - Magnitude Error - % rms M - Vector Error - % rms VCC = 3 V Lo: 240 MHz 10 -10 dBm I/Q DC: 1.5 V Single ended 5 M A 0 100 200 300 400 500 3 2 1 0 0 0.5 3 2 1 1 0 PI/Qin - I/Q Input signal - mVp-p fLO - Lo Input Frequency - MHz 8 Data Sheet P10807EJ3V0DS00 PC8105GR TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM REF 0.0 dBm 10 dB/ ATT 10 dB RBW 1 kHz VBW 1 kHz SWP 2.0 s CENTER 240.0000 MHz SPAN 200.0 kHz TYPICAL /4 DQPSK MODULATION OUTPUT SPECTRUM REF -10.0 dBm 10 dB/ ATT 0 dB MARKER 239.100 MHz 68.75 dB 1 2 3 4 TYPICAL /4 DQPSK MODULATION OUTPUT SPECTRUM REF -10.0 dBm 10 dB/ ATT 0 dB MARKER 289.9000 MHz 76.50 dB 2 3 ADJ BS 192 kHz DL -10.0 dBm ADJ BS 21.0 kHz DL -10.0 dBm 1 4 RBW 3 kHz VBW 10 kHz SWP 5.0 s CENTER 240.000 MHz SPAN 2.000 MHz RBW 3 kHz VBW 3 kHz SWP 5.0 s CENTER 240.0000 MHz SPAN 500 kHz Multi Marker List No.1: 239.100 MHz -68.75 dB No.2: 239.400 MHz -68.25 dB No.3: 240.600 MHz -68.25 dB No.4: 240.900 MHz -69.00 dB Multi Marker List No.1: 239.9000 MHz -76.50 dB No.2: 239.9500 MHz -70.50 dB No.3: 240.0500 MHz -71.00 dB No.4: 240.1000 MHz -75.75 dB Data Sheet P10807EJ3V0DS00 9 PC8105GR MODout OUTPUT IMPEDANCE 2; 49.244 13.58 9.0056 nH 240.000 000 MHz MARKER 2 240 MHz 2 3 MOD out Marker 1. 100 MHz 2. 240 MHz 3. 400 MHz 1 START 50.000 000 MHz STOP 500.000 000 MHz LOin INPUT IMPEDANCE 2; 51.727 -2.0059 330.5 pF 240.000 000 MHz MARKER 2 240 MHz Lo in Marker 2 31 1. 100 MHz 2. 240 MHz 3. 400 MHz START 50.000 000 MHz STOP 500.000 000 MHz 10 Data Sheet P10807EJ3V0DS00 PC8105GR TEST CIRCUIT fMOD out = 100 ~ 400 MHz S.P.A VCC 10 k 1 000 pF 16 VCC 15 Power Save 14 GND 13 GND 12 MOD out 11 NC 10 NC Q 9 NC GND GND Lo in Lo in LO S.G 1 2 Open 3 4 5 Q I I 6 7 8 1 000 pF fLO = 100 ~ 400 MHz PIN = -10 dBm I I Q Q I/Q Signal Generator f : DC to hundreds kHz A : 0.5 Vp-p (I, Q only) V : 1.5 V (I, I, Q, Q) Data Sheet P10807EJ3V0DS00 11 PC8105GR TEST BOARD VCC 10 000 pF P. S. 10 000 pF I F OUT PC8105GR 1 000 pF 10 k LO IN 1 000 pF 1 1 000 pF I IN Q IN 10 000 pF 10 000 pF I Q 12 Data Sheet P10807EJ3V0DS00 PC8105GR PACKAGE DIMENSIONS 16 PIN PLASTIC SHRINK SOP (225 mil) (UNIT: mm) 16 9 detail of lead end 5 5 1 5.2 0.3 8 6.2 0.3 1.565 0.235 1.44 4.4 0.2 0.9 0.2 S 0.5 0.2 0.17 +0.08 -0.07 0.65 0.22 0.08 0.125 0.075 0.475 MAX. 0.10 M 0.10 S NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. Data Sheet P10807EJ3V0DS00 13 PC8105GR NOTE ON CORRECT USE (1) Observe precautions for handling because of electrostatic sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor (e.g. 1 000 pF) to the VCC pin. (5) I, Q DC offset voltage should be same as the I, Q DC offset voltage (to prevent changing the local leak level with power save control.) RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. PC8105GR Soldering process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235 C or below, Reflow time: 30 seconds or below (210 C or higher), * Number of reflow process: 3, Exposure limit : None Peak package's surface temperature: 215 C or below, Reflow time: 30 seconds or below (200 C or higher), * Number of reflow process: 3, Exposure limit : None Solder temperature: 260 C or below Flow time: 10 seconds or below, * Number of reflow process: 1, Exposure limit : None Terminal temperature: 300 C or below Flow time: 3 seconds/pin or below, * Exposure limit : None Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating method *: Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less. Note: Apply only a single process at once, except for "Partial heating method". For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 14 Data Sheet P10807EJ3V0DS00 PC8105GR [MEMO] Data Sheet P10807EJ3V0DS00 15 PC8105GR * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
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